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LT3478/LT3478-1
APPLICATIO S I FOR ATIO
Local heating from the nearby inductor and Schottky diode
will also add to the ?nal junction temperature of the IC.
Based on empirical measurements, the effect of diode and
inductor heating on the LT3478-1 junction temperature
can be approximated as:
Δ T J (LT3478-1) = 5°C/W ? (P DIODE + P INDUCTOR )
P DIODE = (1 – D) ? V F ? I L(AVE)
1 – D = 0.316
V F = 0.5V
I L(AVE) = 2.41
P DIODE = 0.316 ? 0.5 ? 2.41 = 0.381W
P INDUCTOR = I L(AVE)2 ? DCR
DCR = inductor DC resistance (assume 0.05 Ω )
P INDUCTOR = (2.41) 2 ? 0.05 = 0.29W
The LT3478/LT3478-1 use a thermally enhanced FE pack-
age. With proper soldering to the Exposed Pad on the
underside of the package combined with a full copper plane
underneath the device, thermal resistance ( θ JA ) will be
about 35°C/W. For an ambient temperature of T A = 70°C,
the junction temperature of the LT3478-1 for the example
application described above, can be calculated as:
T J (LT3478-1)
= T A + θ JA (P TOT ) + 5(P DIODE + P INDUCTOR )
= 70 + 35(1.25) + 5(0.671)
= 70 + 44 + 4
= 118°C
In the above example, ef?ciency was initially assumed to
be η = 0.89. A lower ef?ciency ( η ) for the converter will
increase I L(AVE) and hence increase the calculated value
for T J . η can be calculated as:
η = P OUT /(P OUT + P LOSS )
If an application is built, the inductor current can be mea-
sured and a new value for junction temperature estimated.
Ideally a thermal measurement should be made to achieve
the greatest accuracy for T J .
Note: The junction temperature of the IC can be reduced
if a lower V IN supply is available – separate from the
inductor supply V S . In the above example, driving V IN
from an available 3V source (instead of V S = 8V) reduces
input quiescent losses in item(4) from 0.597W to 0.224W,
resulting in a reduction of T J from 118°C to 105°C.
Layout Considerations
As with all switching regulators, careful attention must be
given to PCB layout and component placement to achieve
optimal thermal,electrical and noise performance (Figure
12). The exposed pad of the LT3478/LT3478-1 (Pin 17)
is the only GND connection for the IC. The exposed pad
should be soldered to a continuous copper ground plane
underneath the device to reduce die temperature and
maximize the power capability of the IC. The ground path
for the R T resistor and V C capacitor should be taken from
nearby the analog ground connection to the exposed pad
(near Pin 9) separate from the power ground connection
to the exposed pad (near Pin 16). The bypass capacitor
for V IN should be placed as close as possible to the V IN
pin and the analog ground connection. SW pin voltage rise
and fall times are designed to be as short as possible for
maximum ef?ciency. To reduce the effects of both radiated
and conducted noise, the area of the SW trace should be
kept as small as possible. Use a ground plane under the
switching regulator to minimize interplane coupling. The
schottky diode and output capacitor should be placed as
close as possible to the SW node to minimize this high
frequency switching path. To minimize LED current sensing
errors for the LT3478, the terminals of the external sense
resistor R SENSE should be tracked to the V OUT and LED
pins separate from any high current paths.
P OUT = V OUT ? I LED = 17.15W
P LOSS (estimated) = P IC + P DIODE + P INDUCTOR = 1.92W
η = 17.15/(17.15 + 1.92) = 0.9
34781f
18
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